1. Technical Field
The present disclosure relates to electronic packages, and, more particularly, to a substrate structure, an electronic package and a method for fabricating the electronic package.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a 3D chip stacking-type electronic package 1 according to the prior art.
Referring to FIG. 1A, a silicon substrate 10 having a chip mounting side 10a and an opposite external connection side 10b is provided, and a plurality of vias 100 are formed on the chip mounting side 10a of the silicon substrate 10.
Referring to FIG. 1B, an insulating material 102 and a conductive material such as copper are filled in the vias 100 to form a plurality of through silicon vias (TSVs) 101. Then, a redistribution layer (RDL) structure is formed on the chip mounting side 10a of the silicon substrate 10 and electrically connected to the TSVs 101.
In the formation of the RDL structure, a dielectric layer 11 is first formed on the chip mounting side 10a of the silicon substrate 10; then a circuit layer 12 is formed on the dielectric layer 11, wherein the circuit layer 12 has a plurality of conductive vias 120 formed in the dielectric layer 11 and electrically connected to the TSVs 101; then an insulating layer 13 is formed on the dielectric layer 11 and the circuit layer 12, with a portion of the circuit layer 12 exposed; and then a plurality of first conductive elements 14 such as solder bumps are bonded to the exposed portions of the circuit layer 12.
Referring to FIG. 1C, a temporary carrier 40 made of, for example, glass is bonded to the insulating layer 13 on the chip mounting side 10a through an adhesive 400, and then a portion of the silicon substrate 10 at the external connection side 10b is removed by grinding, so as to form an external connection side 10b′ exposing one end surfaces of the TSVs 101.
The silicon substrate 10 has a thickness h of about 700 to 750 μm before the grinding process (shown in FIG. 1B) is performed and a thickness h′ of 100 μm after the grinding process (shown in FIG. 1C) is performed. Generally, the silicon substrate 10 is ground by a mechanical grinding process to a thickness of 102 to 105 μm first, and then ground by a chemical-mechanical polishing (CMP) process to 100 μm.
The thickness t of the adhesive 400 is 50 μm, and is limited by a total thickness variation (TTV) of the adhesive 400. For example, referring to FIG. 1C′, if the TTV of the adhesive 400 is too large (for example, about 10 μm), the silicon substrate 10 will be tilted with one side higher than the other. As such, the silicon substrate 10 is likely cracked during the grinding process. In addition, after the grinding process is performed, only a portion of the TSVs 101 is exposed, with the other TSVs 101 unexposed.
Furthermore, limited by the thickness h′ of 100 μm of the silicon substrate 10 after the grinding process is performed, the TSVs 101 have a certain depth d of about 100 μm. Therefore, the depth to width ratio of the TSVs 101 is limited to 100 μm/10 μm (i.e., the TSVs 101 have a depth of 100 μm and a width w of 10 μm).
In addition, the TSVs 101 having a depth of 10 μm cannot be mass produced due to a high fabrication cost. Since the TTV of the adhesive 400 reaches about 10 μm, the silicon substrate 10 can only be ground by the grinding process (including the mechanical grinding and CMP processes) to the thickness h′ of 100 μm and then a wet etching process is required to remove the silicon substrate 10 by a thickness h″ of about 90 μm so as to expose the TSVs 101. However, the wet etching process is time-consuming and needs a large amount of etching solution, thus increasing the fabrication cost.
Referring to FIG. 1D, an insulating layer 15 is formed on the external connection side 10b′ of the silicon substrate 10, with the end surfaces of the TSVs 101 exposed. Then, a plurality of second conductive elements 16 are formed on the end surfaces of the TSVs 101 and are electrically connected to the TSVs 101. The second conductive elements 16 can include a solder material or can be copper bumps. Further, an under bump metallurgy (UBM) layer 160 can be optionally formed below the second conductive elements 16.
Referring to FIG. 1E, a singulation process is performed along cutting paths L of FIG. 1D to obtain a plurality of silicon interposers 1a. Then, such a silicon interposer 1a is disposed on a packaging substrate 19 through the second conductive elements 16. The packaging substrate 19 has a plurality of conductive pads 190 electrically connected to the TSVs 101 through the second conductive elements 16, and the conductive pads 190 have a large pitch therebetween. Subsequently, an underfill 191 is formed between the silicon interposer 1a and the packaging substrate 19 to encapsulate the second conductive elements 16.
Referring to FIG. 1F, a plurality of electronic elements 17 such as semiconductor chips are disposed on the first conductive elements 14 so as to be electrically connected to the circuit layer 12. The electronic elements 17 are bonded to the first conductive elements 14 in a flip-chip manner, and an underfill 171 is formed between the electronic elements 17 and the silicon interposer 1a to encapsulate the first conductive elements 14. The electronic elements 17 have a plurality of electrode pads having a small pitch therebetween.
Then, an encapsulant 18 is formed on the packaging substrate 19 to encapsulate the electronic elements 17 and the silicon interposer 1a. 
A plurality of solder balls 192 are formed on a lower side of the packaging substrate 19 for mounting an electronic device, for example, a circuit board (not shown). As such, an electronic package 1 is obtained.
In the electronic package 1, the silicon interposer 1a serves as a signal transmission medium between the electronic elements 17 and the packaging substrate 19. To achieve a suitable silicon interposer 1a, the TSVs 101 must be controlled to have a certain depth to width ratio (100 μm/10 μm), which, however, consumes a large amount of time and chemical agent and incurs a high fabrication cost.
Further, during the CMP process, copper ions of the TSVs 101 can diffuse into the silicon substrate 10 and cause a bridging or leakage problem between the TSVs 101.
Furthermore, since a short circuit likely occurs between the ball-shaped second conductive elements 16 having a small pitch therebetween, the density of the second conductive elements 16 is limited.
On the other hand, if the silicon interposer 1a is formed with conductive posts instead of the second conductive elements 16, the silicon interposer 1a needs to be disposed in an electroplating bath, which increases not only the process difficulty but also the risk of damage of the silicon interposer 1a. Therefore, it is difficult to achieve a high pin count for the silicon interposer 1a and hence the function or performance of end products is limited.
Therefore, how to overcome the above-described drawbacks has become critical.